Literature comparison · published 2023 – Oct 2026

Benchmarks for analog circuit design automation

This page compares 38 published benchmarks and datasets for analog circuit design with our work (last row, highlighted). It covers every benchmark we found at the EDA venues (DAC, ICCAD, DATE, ASP-DAC) and the ML venues (NeurIPS, ICML, ICLR), plus widely used or layout-related ones from other venues and workshops.

Each row answers the same questions: what one entry contains, whether the goal of the design is written down, and whether there is a netlist, a layout, a simulation setup and natural-language text. It also says where the data came from. Every name links to the paper, and the code too where there is one.

Yes Partly / limited / not released No

What the 38 benchmarks cover

The table

In the quick view, hover over a dot for its explanation, or switch to full details. Venues were checked against the official proceedings, conference programs or DOIs. Workshop papers and preprints are labelled as such. Where only an abstract is public, the cells say what could not be verified.

What earlier work covers

  • Topology generation (OCB, LaMAGIC, AnalogGenie, OpenCircuit, DiffCkt, the DATE 2024 op-amp library): circuits as netlists or graphs, with simulated performance as labels. None of them includes a layout.
  • Sizing (AnalogGym, AMS-SizingBench, ACOB, threshold-spec suite, FALCON, ZeroSim, AICircuit, Opera): a fixed circuit, a testbench and targets to meet. These stop at the schematic; FALCON only adds an area formula.
  • Reading schematics and answering questions (Masala-CHAI, AMSNet, SINA, AnalogRetriever, CircuitSense, AMSbench, MMCircuitEval, ChipVQA, MuaLLM): images, netlists and text, mostly without simulation.
  • LLM design tasks (AnalogCoder, SAFTAC, Long-Horizon Analog Design Bench, NetlistBench, SGAnalog): a natural-language task, an answer netlist and a checking testbench, all at the schematic level.
  • Layout (OSIRIS, THEIA, ParasGB, GLayout NL-to-layout, Trace-Repair-Verify, LayoutCopilot, AMS-IO-Bench, CTU placement): only OSIRIS and THEIA release layout files. Both are SKY130 only and are built from a handful of fixed circuit templates.

The gaps

  • Specification to verified layout is missing. Of the 38, only OSIRIS releases layouts with post-layout simulation, and it has no performance targets to meet. Every benchmark with performance targets releases nothing beyond the schematic.
  • One process only. None of the 38 offers two or more real processes that can actually be used; some name commercial nodes that are not provided. Every released layout dataset is SKY130-only.
  • Layout intent is rarely explicit or checkable. Where layout intent exists, it is free text (GLayout NL-to-layout, LayoutCopilot), a list of matching pairs (OSIRIS) or abstract geometry rules (CTU placement). It is not an object that a tool can check against the circuit before drawing.
  • Little control over layout decisions. Few datasets vary one layout decision at a time and measure what it does to area and performance. OSIRIS varies finger order and placement, but on 5 circuits with fixed sizes.
  • Quality of auto-extracted data. Many netlist datasets are machine-extracted from images and never simulated. A 2026 study found that only 22% of Masala-CHAI netlists compile.

What this work adds

  • From frozen specs to verified layouts: 547 entries, each with a sized netlist, a testbench and specs frozen before layout. All 6,159 layouts go through the official DRC deck, LVS, a size check, R+C extraction and post-layout simulation.
  • Three open processes: SKY130, GF180MCU and IHP SG13G2, at 12 sizes per circuit.
  • Layout intent a tool can check: the sharing plan lists finger order, source/drain sides, shared strips and gate straps. It is checked before drawing, and sharing is measured on the drawn shapes.
  • Controlled variation: 4 fixed sharing modes on every entry; up to 64 plans built and checked for each of 56 tasks; 168 language-model sessions in which every proposal is checked.
  • Traceable sources: every circuit maps to an AnalogGenie entry and a textbook page (17 matched exactly, 1 written from Gray et al.).

What is still open

  • Natural language: we have no per-entry text description. AnalogCoder, AMS-SizingBench and Long-Horizon Analog Design Bench do. Adding written specs and intent per entry would make ours an LLM benchmark from text to layout.
  • Scale: our benchmark has 18 topologies, against 3,350 in AnalogGenie. LDOs, bandgaps and comparators are missing.
  • More layout decisions: placement, routing and matching constraints such as common-centroid. OSIRIS already records matching pairs.
  • Matching and corners: no Monte Carlo or layout-dependent-effect analysis yet.
  • Release form: our GDS is rebuilt from recorded plans rather than shipped. Rendered layout images (as in THEIA) would enable vision tasks.
  • Real silicon and expert layouts: SGAnalog and ParasGB start from taped-out designs; we have no hand-drawn references.

Screened but not in the table

How to read the table

Design intent
What the designer wants, written down in the benchmark: numeric specifications, a natural-language requirement, or layout constraints. Partly means the goal is only implied: each entry's own simulated numbers, a single score, or a goal for only some items.
Netlist
The list of devices and connections. Partly means graphs, behavioural blocks or ideal parts instead of transistors, a netlist for only some items, or one that is not released.
Layout
The drawn shapes a factory manufactures (GDS). Partly means layout-related data without released geometry: constraints, parasitic values, placement problems, pictures, or layouts made in the paper but not released.
Testbench
A simulation set-up that measures performance. Partly means it is not released, needs a commercial simulator, or covers only some items.
Natural language
Human-readable text per entry (a task, question or description). Partly means template text or text for only some items.
Post-layout sim
Released layouts that are extracted and simulated. Partly means it was done in the paper but not released.
Processes
Yes means two or more real processes are usable. Partly means several are named but only one is open or usable.
Open source
Yes means public with a license. Partly means public without a license, partly released or gated. No means not released.

Screened on 14 October 2026. Counts are quoted from the papers; when the released files differ, both numbers are given in the details. For 2026 papers whose full text is not yet public, only the abstract was checked.